As operating frequencies of large-scale integration (LSI) circuits improve, the importance of addressing electromagnetic interference (EMI) is growing. An SSCG phase-locked loop (PLL) is often included in digital consumer devices such as printers and personal computers, as measures against EMI. However, since an internal clock of an LSI circuit has a certain frequency, the spectrum exhibits a peak at a certain frequency, thereby causing radiated electromagnetic noise. By slightly changing such clock frequency with an SSCG, energy of the spectrum can be distributed to other frequencies and the peak at such certain frequency can therefore be reduced.
Patent Document 1 discloses a conventional SSCG, and FIG. 8 is a block diagram of a conventional SSCG disclosed in FIG. 6 of Patent Document 1. The clock generator of FIG. 8 includes programmable counters (or frequency dividers) 35 and 42 on the reference clock side and the feedback loop side, respectively. The clock generator changes the frequency of an operation clock by changing a frequency division ratio of the programmable counters 35 and 42 in the feedback loop in the PLL. The frequency division ratios of the programmable counters 35 and 42 are set by lookup tables 46 and 47, respectively. By changing the frequency division ratios of the programmable counters 35 and 42 with the lookup tables 46 and 47 during a PLL operation, the spectrum of a clock outputted from a voltage-controlled oscillator (VCO) is spread.
FIG. 9 is a block diagram of another conventional SSCG disclosed in FIG. 7 of Patent Document 1. Based on this clock generator, an analog modulation circuit 52 generates a waveform for modulation, which is added to a control voltage applied to a second VCO 51, to spread the spectrum of a clock outputted from the second VCO 51. The analog modulation circuit 52 uses a triangular waveform generator and a log anti-log amplifier to generate the waveform for modulation. Based on the clock generator of FIG. 9, a phase detector 37 compares phases, and a filter 38 smoothes the comparison results. The modulation voltage generated by the analog modulation circuit 52 is added to the output from the filter 38 to supply the control voltage to the second VCO 51.
Further, FIG. 10 is a block diagram of still another conventional SSCG disclosed in FIG. 8 of Patent Document 1. In FIG. 10, a reference clock oscillation circuit 72 including an LC circuit is used, and an oscillation frequency of the reference clock oscillation circuit 72 is directly modulated by the analog modulation circuit 52.
Furthermore, FIG. 11 is still another conventional SSCG disclosed in FIG. 9 of Patent Document 1. In FIG. 11, instead of the analog modulation circuit 52 of FIG. 9, a read only memory (ROM) 82 and a digital-to-analog converter 83 are used to generate a modulation waveform. The modulation waveform is added to a control voltage outputted from the filter 38 to modulate an oscillation frequency of the second VCO 51. As in the SSCG in FIG. 11, after the phase detector 37 compares phases and the filter 38 smoothes the comparison results, the output from the filter 38 is added to the modulation voltage outputted from the digital-to-analog converter 83.
Patent Document 1: U.S. Pat. No. 5,488,627